Jednym z ciekawszych podrzędnych ogłoszeń wyjdzie numerów referencyjnych EPYC Intela była zjeżdżalnia na „pędu” nowej platformy Intel Xeon Scalable użyciem rdzeni Skylake-SP. Alongside the notice of ‘110+ performance world records’ and ‘200 OEM systems shipping’ was a side note on the next iteration of Xeon-D, which will be getting the latest enterprise Skylake-SP cores.
Xeon-D is a platform that sits in an odd position in Intel’s product portfolio. The first generation launched in November 2015, based on Broadwell, paired up to 8 Broadwell cores with 32 pasy z PCIe 3.0 and dual 10-gigabit Ethernet controllers. With a thermal design limit of 45W, memory support up to 128GB of ECC, speeds up to 2.7 GHz, and a BGA-only design, the Xeon-D platform found a place in home servers, sieci, high-end NAS designs, hyper-scale embedded implementations, and was a general all-around interesting part that never really breached the light of day for most consumers. Na pierwszy rzut oka, it seemed like a really nice implementation of Broadwell and features that Intel wanted to remain under the purview of its embedded segmentation, rather than launch it into other segments. W lutym 2016, Intel then upgraded the stack to include 16-core versions at 65W, z do 2.4 GHz turbo. The 16-core Xeon D-1581 became very popular with certain large companies. Niezależnie od small secondary launch of networking focused parts in July this year, Xeon-D users have been waiting to hear about an upgrade (and to what).
Within the single bullet point, Intel confirms that the next generation of Xeon D SoCs will be coming in early 2018 (followed by Xeon-SP + FPGA), and that the cores in Xeon D would be of a Skylake-SP flavor.
The cores are the interesting part here. The old Xeon-D were standard Broadwell cores, when there was no separation between the standard mainstream Core microarchitecture and the enterprise microarchitecture design. Z Skylake, we have two versions: Skylake-S, which uses a standard ring bus and a known L2/L3 cache hierarchy, and Skylake-SP which uses a mesh networking topology to connect the cores, a larger L2 cache at the expense of the L3 cache (which becomes a non-inclusive victim cache), and also has a substantial AVX-512 unit inside. That AVX-512 unit accounts for almost 20% of the core size, so despite moving from 14nm on the Broadwell cores to 14+ on the Skylake-SP cores, overall the new cores in Xeon-D are going to be larger.
Ogólny, it means that we might see the second generation of Xeon-D still end up limited to 16 rdzenie, but in a new mesh configuration with AVX-512 support. Czyli, Oczywiście, if Intel wants to keep the Xeon-D platform to the 45W/65W TDP of the first generation. There is also no word on exactly what other features are going to be present, such as 10G networking, or even some of Intel’s other networking features like QuickAssist Technology. PCIe lane counts have a question mark, although memory is likely still to be ECC capable DDR4. Whether that means anything above RDIMMs, or even if the maximum capacity is set to increase, is still up for questioning.
It is worth noting, ślają Patrick at ServeTheHome, that Intel has stated ‘early 2018’ rather than simply ‘Q1 2018’, which means that Intel has room to let the launch slip. Intel’s embedded parts have had a history of slipping their original launch dates, such as the Intel C3000 Denverton launch which has been pushed back almost a year. Patrick also points out that delays may push others onto 16-core Atom C3000 parts instead, although having microarchitecture parity with the Xeon-SP line of processors allows for live migration of virtual machines, allowing them to be run in embedded systems.
Top Image: an example first-generation Xeon-D system